In the present description, a frame is defined as set of successive items of data and a scene as a set of successive frames. In the specific case of video, a frame is an image.
The quantity of information (entropy) contained in a signal can vary hugely in time. For example, in the case of a video signal, it is possible to switch from a static scene containing smooth textures to a scene featuring many moving objects and complex textures. In this case, a significant increase of the complexity of the scene may be observed, and therefore of the quantity of information.
When compression techniques are used, this natural variability has two consequences:                first of all, the bit rate of data generated by the encoder varies according to the scene;        then, depending on the application strategy chosen, the time required for the encoding of each frame can vary.        
Solutions have been developed to overcome these two problems.
Bit rate control techniques permit the output bit rate of the encoder to be regulated. It is possible to ensure either a constant bit rate or a variable bit rate. In both cases, an external constraint is respected, such as for example the physical capacity of a communication channel. If this external constraint varies in time, then this is the case of the variable bit rate (VBR). The control of the bit rate is based on the use of modelling of the emission buffer memory, which is also called “emission buffer” or even EBV (Emission Buffer Verifier). The emission buffer memory is also called VBV (for Video Buffer Verifier) in the case of the compression of a video signal or “reservoir-bit” in the case of the compression of an audio signal.
Further details on bit rate control may be found in: “Efficient algorithms for MPEG video compression”, Dzung Tien Hoang, Jeffrey Scott Vitter, WILEY, 2002.
To ensure timely constant encoding per frame, the most simple solution consists of over sizing the equipment (processor, FPGA, etc.). However this solution is costly and not optimal, as the equipment is only rarely used to its full capacity. The opposite logic consists of limiting the complexity of the encoder.
In this case, the efficiency of the compression is limited and consequently the quality of the data compressed. Similarly, the equipment is only rarely used to its full capacity. Furthermore, the quality is not optimal in scenes of low complexity.
Ideally, it would be possible to limit the complexity of the encoder simply when the scene is too complex so that it could be processed in real time with the equipment available. Such a dynamic complexity control technique is presented in the patent document WO 03/061298 A1, dated 24 Jul. 2003.
Before resuming this dynamic complexity control technique, one example of a classic real time encoder will be described, based on the FIG. 1. The encoder is synchronised with a discreet clock. This clock is adjusted to the frequency of the frames. For example, at 25 frames per second, the clock will provide a “start” every 40 ms. These clock starts are indexed according to the variable t. The period of the starts, which is to say the duration between two successive starts, is noted P.
The example of the real time encoder of FIG. 1 comprises:                a capture module 1 (for example in the form of a card or an appliance) which captures the input frames and converts them to a format that may be used by the encoding module. For example, a video input may be in the SDI format and the corresponding output in the raw YUV format;        a capture buffer 2 where the frames waiting to be processed by the encoding module are stored. At the instant t, this capture buffer contains Nc(t) frames;        an encoding module 3 (for example in the form of an appliance) which makes the compression. At its input it takes a captured frame and sends to the output a compressed frame. It processes Ve(t) frames per clock period at the instant t;        an output buffer where the compressed frames issued from the encoding module are stored, waiting to be transferred to the emission buffer memory (EBV). At the instant t, this intermediate buffer memory contains No(t) compressed frames;        an emission buffer memory 5 (also called EBV for emission buffer verifier) which is an element that is essential to the correct operation of the bit rate regulation. The EBV, with its bit rate control logic, permits the variation of the size of the compressed frames to be partially compensated, whilst guaranteeing that the bit rate constraint is respected. The role of the bit rate control logic is to ensure that the EBV is never exceeded in capacity. The EBV models a buffer memory which stores the compressed frames until they are transmitted to the communication channel. Each frame that is compressed in the EBV is divided into data packets of a fixed size. At the instant t, the EBV contains Dv(t) data packets.        
The various elements 1 to 5 in the encoder are classically made using computer technology, with one or more elements of equipment (especially memory and processor components) and/or software (programs).
The data transfers, references A to E in FIG. 1, are described below. A data transfer is said to be synchronised if it is aligned with the clock, which is to say if occurs at each start. An unsynchronised data transfer is completely independent of the clock.
Transfer A (synchronised): at each start, a frame leaves the capture module 1 and is stored in the capture buffer memory 2.
Transfer B (unsynchronised): at the instant t, the encoding module 3 takes in input Ve(t) frames per clock period.
Transfer C (non-synchronised): at the instant t, the encoding module 3 also sends to the output Ve(t) compressed frames per clock period.
Transfer D (synchronised): at each start, the EBV 5 takes in input Vo(t) data packets (which generally correspond to one compressed frame).
Transfer E (synchronised): the VBV sends to the output a data packet at each start. It thus guarantees a controlled bit rate on the communication channel. In the case of a constant bit rate (CBR), the size of the data packets is constant and thus the output bit rate is constant.
Classically, the process formed by the set of transfers A to E is controlled by a program run by one or several processors in the encoder.
The function of the two capture buffer 2 and intermediate 4 memories is to compensate the variation in processing time per frame of the encoder (Ve(t)). These two buffer memories are synchronised. When one is emptied, the other is filled. Wherein Mc is the maximum size of each of these two buffer memories. Where: No(t)=Mc−Nc(t).
If the processing time by the encoding module remains greater than P (which is to say if Ve(t)<1) for too long a period, the capture buffer memory is filled. The only way to respect the real time constraint is then to eliminate frames. In the case of video decoding, when the compressed video is decoded and displayed, this is translated by visually unacceptable jerky images.
In order to avoid the suppression of frames, the technique presented in the patent document WO 03/061298 A1 consists of using a complexity control mechanism. This mechanism will now be described in relation to FIG. 2. The encoder comprises the additional following element: a control module 6 (also called RTC, Real-Time Controller) which monitors the filling level Nc(t) of the capture buffer memory 2 (this monitoring is shown by the arrow reference 7). This filling level Nc(t) is the number of frames contained in the capture buffer memory. According to this filling level, it controls the complexity of the encoding module (this control is shown by the arrow reference 8). A series of thresholds with hysteresis are pre-defined. At each filling level of the capture buffer memory 2 corresponds a set of parameters for the encoding module 3. Due to the synchronisation property mentioned above (between the capture buffer memory 2 and the intermediate buffer memory 4), it is not necessary to monitor the filling of the intermediate buffer memory 4.
Unfortunately, the solution presented above is efficient but not optimal for two reasons:                firstly, reducing the complexity of the encoding module 3 implies lowering the quality of the compressed frames;        then, if in spite of the adjustment of the complexity of the encoding module 3, the encoding time is still too long, it may still be necessary to eliminate frames. This problem is that of a complexity peak that is too long.        
By increasing the size of the capture buffer memory 2, it is possible to process longer complexity peaks, or to maintain the quality of the compressed data (for example video) until the complexity peak has passed. However this introduces an extra time to the overall output of the encoder. In fact, the encoder as it is presented introduces a time whose size is at least Mc. Which is to say that if a frame enters the encoder at the instant t, it will leave at the earliest at the instant t+P·Mc. Similarly, each element of the encoder may introduce a time. If De is the time introduced by the encoding module 3 of the encoder and DEBV is the time introduced by the emission buffer memory 5 (EBV), then the time total of the encoder is: D=Mc+De+Debv.